/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved.
 * Description: RDMA npu commonds.
 * Create: 2023-10-11
 */
 
#ifndef ROCE_NPU_CMD_H
#define ROCE_NPU_CMD_H
 
/*
 * Commands between RoCE driver to NPU
 */
enum {
    /* RDMA MIG */
    VROCE_CMD_MIG_DIRTY_DRAIN_NUM = 0x50,
    VROCE_CMD_MIG_DIRTY_DRAIN = 0x51,
    VROCE_CMD_MIG_QUERY_FLOW_HUNG_STATUS = 0x52,
    VROCE_CMD_MIG_RESTORE_DRIVER_COUNTER = 0x53,
    VROCE_CMD_MIG_CACHE_OUT = 0x54,
    VROCE_CMD_MIGR_CMD_ROLLBACK = 0x55,
    VROCE_CMD_MIGR_CMD_QUERY_ROLLBACK = 0x56,
    VROCE_CMD_MIG_TIMER_RESTORE = 0x57,
    VROCE_CMD_MIG_DB_RESTORE = 0x58,
    VROCE_CMD_MIG_FORWARD_ADD_MIG_ENTRY = 0x59,
    VROCE_CMD_MIG_FORWARD_DEL_MIG_ENTRY = 0x5a,
    VROCE_CMD_MIG_FORWARD_DUMP_MIG_ENTRY = 0x5b,
    VROCE_CMD_MIG_FORWARD_UPDATE_MIG_ENTRY = 0x5c,
    VROCE_CMD_MIG_QUERY_GID = 0x5d,
    VROCE_CMD_MIG_UPDATE_GID = 0x5e,
    VROCE_CMD_MIG_MAX = 0x5f,

    /* GID CMD */
    ROCE_CMD_UPDATE_GID = 0x60, /**< Update GID table @see > roce_uni_cmd_update_gid_s */
    ROCE_CMD_QUERY_GID = 0x61, /**< Query GID table @see > roce_uni_cmd_query_gid_s */
    ROCE_CMD_CLEAR_GID = 0x62, /**< Clear GID table @see > roce_uni_cmd_clear_gid_s */

    /* IP CMD */
    VROCE_CMD_ADD_IP_ENTRY = 0x68,
    VROCE_CMD_DEL_IP_ENTRY = 0x69,
    VROCE_CMD_LOOKUP_IP_ENTRY = 0x6a,
    VROCE_CMD_UPDATE_IP_ENTRY = 0x6b,

    /* TPT CMD */
    ROCE_CMD_SW2HW_MPT = 0x70, /**< Init MPT context to HW @see > roce_uni_cmd_mpt_sw2hw_s */
    ROCE_CMD_HW2SW_MPT = 0x71, /**< Deinit MPT context from HW @see > roce_uni_cmd_mpt_hw2sw_s */
    ROCE_CMD_MODIFY_MPT = 0x72, /**< Modify MPT in HW @see > roce_uni_cmd_modify_mpt_s */
    ROCE_CMD_QUERY_MPT = 0x73, /**< Query MPT context from HW @see > roce_uni_cmd_mpt_query_s */
    ROCE_CMD_FLUSH_TPT = 0x74, /**< Unused */
    ROCE_CMD_SYNC_TPT = 0x75, /**< Unused */
 
    /* CQ CMD */
    ROCE_CMD_SW2HW_CQ = 0x80, /**< Init CQ context to HW @see > roce_uni_cmd_create_cq_s */
    ROCE_CMD_RESIZE_CQ = 0x81, /**< Resize CQ and notify HW @see > roce_uni_cmd_resize_cq_s */
    ROCE_CMD_MODIFY_CQ = 0x82, /**< Modify CQ context in HW @see > roce_uni_cmd_modify_cq_s */
    ROCE_CMD_HW2SW_CQ = 0x83, /**< Deinit CQ context from HW @see > roce_uni_cmd_cq_hw2sw_s */
    ROCE_CMD_QUERY_CQ = 0x84, /**< Query CQ context in HW @see > roce_uni_cmd_cq_query_s */
 
    /* SRQ CMD */
    ROCE_CMD_SW2HW_SRQ = 0x90, /**< Init SRQ context to HW @see > roce_uni_cmd_create_srq_s */
    ROCE_CMD_ARM_SRQ = 0x91, /**< Arm SRQ to HW @see > roce_uni_cmd_srq_arm_s */
    ROCE_CMD_HW2SW_SRQ = 0x92, /**< Deinit SRQ context from HW @see > roce_uni_cmd_srq_hw2sw_s */
    ROCE_CMD_QUERY_SRQ = 0x93, /**< Query SRQ context in HW @see > roce_uni_cmd_srq_query_s */
 
    /* QP CMD */
    ROCE_CMD_QP_BASE = 0xa0,
    ROCE_CMD_RST2INIT_QP = 0xa0, /**< Modify QP context from reset to init state @see > roce_uni_cmd_modify_qpc_s */
    ROCE_CMD_INIT2INIT_QP = 0xa1, /**< Modify QP context from init to init state @see > roce_uni_cmd_modify_qpc_s */
    ROCE_CMD_INIT2RTR_QP = 0xa2, /**< Modify QP context from init to rtr state @see > roce_uni_cmd_modify_qpc_s */
    ROCE_CMD_RTR2RTS_QP = 0xa3, /**< Modify QP context from rtr to rts state @see > roce_uni_cmd_modify_qpc_s */
    ROCE_CMD_RTS2RTS_QP = 0xa4, /**< Modify QP context from rts to rts state @see > roce_uni_cmd_modify_qpc_s */
    ROCE_CMD_SQERR2RTS_QP = 0xa5, /**< Modify QP context from sqerr to rts state @see > roce_uni_cmd_modify_qpc_s */
    ROCE_CMD_2ERR_QP = 0xa6, /**< Modify QP context from any state to err state @see > roce_uni_cmd_modify_qpc_s */
    ROCE_CMD_RTS2SQD_QP = 0xa7, /**< Modify QP context from rts to sqd state @see > roce_uni_cmd_qp_modify_rts2sqd_s */
    ROCE_CMD_SQD2SQD_QP = 0xa8, /**< Modify QP context from sqd to sqd state @see > roce_uni_cmd_modify_qpc_s */
    ROCE_CMD_SQD2RTS_QP = 0xa9, /**< Modify QP context from sqd to rts state @see > roce_uni_cmd_modify_qpc_s */
    ROCE_CMD_2RST_QP = 0xaa, /**< Modify QP context from any state to reset state @see > roce_uni_cmd_qp_modify2rst_s */
    ROCE_CMD_QUERY_QP = 0xab, /**< Query QP context from HW @see > roce_uni_cmd_qp_query_s */
    ROCE_CMD_MIRROR_QP = 0xac, /**< Unused */
    ROCE_CMD_MODIFY_HASH_VALUE_QP = 0xad, /**< Unused */
    ROCE_CMD_GET_QP_RX_PORT = 0xae, /**< Unused */
    ROCE_CMD_MODIFY_UDP_SRC_PORT_QP = 0xaf, /**< Unused */
    ROCE_CMD_GET_UDP_SRC_PORT_QP = 0xb0, /**< Unused */
    ROCE_CMD_GET_QP_FUNC_TABLE = 0xb1,
    ROCE_CMD_MODIFY_TCALSS_VALUE_QP = 0xb2,
    ROCE_CMD_QP_MAX = 0xb2,
 
    /* MTT commands */
    ROCE_CMD_QUERY_MTT = 0xc0, /**< Query MTT context from HW @see > roce_uni_cmd_query_mtt_s */
 
    /* DFX commands */
    ROCE_CMD_MODIFY_CONTEXT = 0xd0, /**< Unused */
    ROCE_CMD_EN_QP_CAP_PKT = 0xd1, /**< Unused */
    ROCE_CMD_DIS_QP_CAP_PKT = 0xd2, /**< Unused */
 
    /* CACHE commands */
    ROCE_CMD_MISC_CACHE_INVLD = 0xe0, /**< Invalid QP context cache from HW @see > roce_uni_cmd_qp_cache_invalid_s */
    ROCE_CMD_MISC_CQ_CACHE_INVLD = 0xf0, /**< Invalid CQ context cache from HW @see > roce_uni_cmd_cq_cache_invalid_s */
 
    /* ULP CMD */
    ROCE_CMD_CREAT_SLAVE_QP = 0xf1, /**< Unused */
    ROCE_CMD_QUERY_MASTER_QP_BITMAP = 0xf2, /**< Unused */
    ROCE_CMD_GET_MASTER_QPN = 0xf3, /**< Unused */
    ROCE_CMD_SET_CONN_STAT = 0xf4, /**< Unused */
    ROCE_CMD_DISCONNECT_QP = 0xf5, /**< Unused */
    ROCE_CMD_SET_SHARD_CFG = 0xf6 /**< Unused */
};

enum roce3_cmd_type {
    COMMON_CMD_TX_INFO = 1,
    COMMON_CMD_Q_NUM,
    COMMON_CMD_TX_WQE_INFO,
    COMMON_CMD_TX_MAPPING,
    COMMON_CMD_RX_INFO,
    COMMON_CMD_RX_WQE_INFO,
    COMMON_CMD_RX_CQE_INFO,
    COMMON_CMD_UPRINT_FUNC_EN,
    COMMON_CMD_UPRINT_FUNC_RESET,
    COMMON_CMD_UPRINT_SET_PATH,
    COMMON_CMD_UPRINT_GET_STATISTICS,
    COMMON_CMD_FUNC_TYPE,
    COMMON_CMD_GET_FUNC_IDX,
    COMMON_CMD_GET_INTER_NUM,
    COMMON_CMD_CLOSE_TX_STREAM,
    COMMON_CMD_GET_DRV_VERSION,
    COMMON_CMD_CLEAR_FUNC_STASTIC,
    COMMON_CMD_GET_HW_STATS,
    COMMON_CMD_CLEAR_HW_STATS,
    COMMON_CMD_GET_SELF_TEST_RES,
    COMMON_CMD_GET_CHIP_FAULT_STATS,
    COMMON_CMD_NIC_RSVD1,
    COMMON_CMD_NIC_RSVD2,
    COMMON_CMD_NIC_RSVD3,
    COMMON_CMD_GET_CHIP_ID,
    COMMON_CMD_GET_SINGLE_CARD_INFO,
    COMMON_CMD_GET_FIRMWARE_ACTIVE_STATUS,
    COMMON_CMD_ROCE_DFX_FUNC,
    COMMON_CMD_GET_DEVICE_ID,
    COMMON_CMD_GET_PF_DEV_INFO,
    COMMON_CMD_CMD_FREE_MEM,
    COMMON_CMD_GET_LOOPBACK_MODE = 32,
    COMMON_CMD_SET_LOOPBACK_MODE,
    COMMON_CMD_SET_LINK_MODE,
    COMMON_CMD_SET_PF_BW_LIMIT,
    COMMON_CMD_GET_PF_BW_LIMIT,
    COMMON_CMD_ROCE_CMD,
    COMMON_CMD_GET_POLL_WEIGHT,
    COMMON_CMD_SET_POLL_WEIGHT,
    COMMON_CMD_GET_HOMOLOGUE,
    COMMON_CMD_SET_HOMOLOGUE,
    COMMON_CMD_GET_SSET_COUNT,
    COMMON_CMD_GET_SSET_ITEMS,
    COMMON_CMD_IS_DRV_IN_VM,
    COMMON_CMD_LRO_ADPT_MGMT,
    COMMON_CMD_SET_INTER_COAL_PARAM,
    COMMON_CMD_GET_INTER_COAL_PARAM,
    COMMON_CMD_GET_CHIP_INFO,
    COMMON_CMD_GET_NIC_STATS_LEN,
    COMMON_CMD_GET_NIC_STATS_STRING,
    COMMON_CMD_GET_NIC_STATS_INFO,
    COMMON_CMD_GET_PF_ID,
    COMMON_CMD_NIC_RSVD4,
    COMMON_CMD_NIC_RSVD5,
    COMMON_CMD_DCB_QOS_INFO,
    COMMON_CMD_DCB_PFC_STATE,
    COMMON_CMD_DCB_ETS_STATE,
    COMMON_CMD_DCB_STATE,
    COMMON_CMD_QOS_DEV,
    COMMON_CMD_NIC_RSVD7,
    COMMON_CMD_GET_ULD_DEV_NAME,

    COMMON_CMD_RSS_CFG = 0x40,
    COMMON_CMD_RSS_INDIR,
    COMMON_CMD_PORT_ID,

    COMMON_CMD_GET_FUNC_CAP = 0x50,

    COMMON_CMD_GET_WIN_STAT = 0x60,
    COMMON_CMD_WIN_CSR_READ = 0x61,
    COMMON_CMD_WIN_CSR_WRITE = 0x62,
    COMMON_CMD_WIN_API_CMD_RD = 0x63,

    COMMON_CMD_VM_COMPAT_TEST = 0xFF
};

enum roce3_gid_type {
    ROCE_IPv4_ROCEv2_GID = 0,
    ROCE_IPv6_ROCEv2_GID = 1,
    ROCE_ROCEv1_GID = 2,
    ROCE_INV_GID
};

#endif /* ROCE_PUB_CMD_H */
